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Simon Waters wrote: > > Based on output of dmidecode I think it is a bug in lshw, and it is > reporting the maximum supported L3 cache the CPU architecture could > support where it should be reporting the installed sized of L3 cache, > since the former figure isn't terribly useful since you can't exactly > add it to the CPU after manufacture. Next release (2.14 as opposed to 2.13 in Lenny) of lshw doesn't report the L3 cache. -- The Mailing List for the Devon & Cornwall LUG http://mailman.dclug.org.uk/listinfo/list FAQ: http://www.dcglug.org.uk/linux_adm/list-faq.html