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Gordon Henderson wrote: > > There are versions of the Xeon with no L3 cache present - I suspect > you've got one - like me: Based on output of dmidecode I think it is a bug in lshw, and it is reporting the maximum supported L3 cache the CPU architecture could support where it should be reporting the installed sized of L3 cache, since the former figure isn't terribly useful since you can't exactly add it to the CPU after manufacture. I'll file that as a bug report, and see if anyone more knowledgeable shouts! Thanks Gordon. Simon -- The Mailing List for the Devon & Cornwall LUG http://mailman.dclug.org.uk/listinfo/list FAQ: http://www.dcglug.org.uk/linux_adm/list-faq.html