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On Sun, 24 Apr 2022, Tom via list wrote:
http://tice.sea.eseo.fr/riscv/and https://riscv.org/news/2020/06/emulsiv-a-visual-simulator-for-teaching-computer-architecture-using-the-risc-v-instruction-set-guillaume-savation/for an intro video!
Oh, very nice.I've been dabbling in RISC-V recently myself - after the horrors of the 65816 I'm finding it a real joy to use (writing assembler for anyway). There is a bit of a gap in the market though - at one end you have some very nice little 32-bit systems, aimed at the microcontroller/IoT market with limited RAM (32KB if you're lucky) and then almost nothing until you get to 64-bit systems with GB of RAM aimed at running Linux!
I've found one exception which is the ESP32-C3 system - which has 400KB of RAM and I have a couple (Lookup the M5Stamp Pico systems if you're into that thing) but they're not quite what I want, so I have been "forced" into the world of FPGAs, Verilig, VHDL and bludgeoning cores into making my own SoC with a RV-32IM core, I2C, SPI, UART and 1MB of RAM - just so I can run my little BCPL operating system...
FWIW: I wrote a RISC-V emulator in BCPL on my existing system then used that to write the byecode interpreter that BCPL compiles into then used that to run my BCPL operating system... It wasn't fast, but it got there in the end and proved the concept, so when I had real RV hardware the initial bootstrap of my OS was relatively easy.
Oh well, the things we do for fun! Cheers, Gordon -- The Mailing List for the Devon & Cornwall LUG https://mailman.dcglug.org.uk/listinfo/list FAQ: https://www.dcglug.org.uk/faq/